An MOS transistor, whether an NMOS or PMOS transistor, conventionally has source and drain regions as well as a gate insulated from the substrate by a dielectric region, commonly referred to by the person skilled in the art by the term “gate oxide”.
Doped polysilicon has for a long time been used as a gate material, in particular for the 120 nm to 450 nm technology nodes. As a semiconductor material, its Fermi level is adjustable throughout the bandgap of silicon by implantation of dopants, which makes it possible to adjust the desired electrical characteristics, in particular the threshold voltage.
Originally, silicon dioxide (SiO2) was used as the gate oxide. With technical development, however, the thickness of the gate oxide is decreasing, the effect of which is to increase the tunneling leakage current. It has therefore been necessary to use a gate oxide with a higher dielectric permittivity. This is the reason why the gate oxide was firstly nitrided in order to become silicon oxynitride (SiON), which makes it possible to increase its dielectric constant.
However, transistors having polysilicon gates as well as gate oxides formed by SiON have a high leakage current associated with a phenomenon of depletion of the polysilicon, which leads to high threshold voltages for the transistors.
It was then envisaged to insert, between the silicon oxynitride and the polysilicon gate, a material with high permittivity (referred to as a “high-K” material) having dielectric constants K of more than 10.
This makes it possible to reduce the tunneling leakage current but leaves remaining the problem of the phenomenon of depletion of the polysilicon gate, therefore still leading to a high threshold voltage.
In order to reduce the threshold voltage of the transistor, it is then proposed, in particular for technology nodes of 28 nanometers and less, to replace the polysilicon gate with a metal layer of a “mid-gap” material, that is to say one whose work function lies substantially between the level of the conduction band of silicon and the level of the valence band of silicon.
There are principally two solutions for producing a metal gate.
A first solution consists in depositing the dielectric region/metal gate stack after production of the doped source and drain regions and the dopant activation anneal. This is a so-called “gate last” architecture, according to the terminology well known to the person skilled in the art.
This makes it possible to widen the range of possible metals having a high work function in order to adjust the characteristics of the device. On the other hand, such a manufacturing method is significantly more complex and the design rules of the circuits are more constringent.
Another solution consists in producing the metal gate before production of the doped source and drain regions and the dopant activation anneal. Such an architecture is referred to as “gate first”, according to terminology well known to the person skilled in the art.
Such an architecture simplifies the manufacture and design of the circuits. However, it means that the gate/dielectric stack undergoes the dopant activation anneal at more than 1000° C. This is a major constraint which limits the choice of the materials. By way of nonlimiting example, the pairing TiN/HfSiON has been adopted for its thermal stability, titanium nitride having a work function of close to 4.6 eV when it is annealed at more than 1000° C.
Such a gate stack thus makes it possible to reduce the leakage current and avoid the phenomenon of depletion, which makes it possible to reduce the threshold voltage of the transistor.